Mesh architecture allows for massively scalable multi-core chips.
Start-up chip firm Tilera is scheduled to release a low power, high performance 64-core processor later today.
Tilera claims that its new TILE64 processor can out-perform Intel's Xeon by 1,000 per cent on some workloads, while consuming only one third of the power.
Scheduled to be unveiled at the Hot Chips conference at Stanford University in Silicon Valley, the processor targets embedded applications in communications devices and switches as well as appliances for encoding high-definition video streams.
Tilera claimed that the chip will allow the Snort network security application to scan 10Gb of data traffic for malware and other suspicious activity in the same time that an Intel Xeon chip could scan 1Gb.
The chip is also aiming for the digital signal processing space, where it could be used to encode high-definition video streams at a much faster speed than current technologies.
Tilera claimed that its chip performs 40 times faster than the leading Motorola chip in the space, the TMS320DM648.
The start-up will start shipping a 600MHz model at US$435 (AUD$540), comparable to the cost of a mid-range Intel quad-core Xeon.
Tilera will also ship a 1GHz model. A 32-core chip is scheduled for release by the middle of next year and a 120-core version late next year.
The secret to the processor lies in its mesh interconnect, a new way to connect multiple cores on the chip.
Bob Doud, director of marketing at Tilera, claimed that the architecture will allow the "next decade of processor and multi-core development".
"It allows us to come out with 64 cores which nobody else has done. And we are able to scale up to hundreds and even thousands of cores without radically re-architecting this basic design," Doud said.
Nathan Brookwood, an analyst with Insight64, acknowledged that the chip's design is one of its strong points.
"The architecture is going to lend itself to scalability in a way that most other multi-core designs that I have seen so far do not," Brookwood said.
Processors hit a bottleneck as they gain cores, because data has to be transported from the processing cores to controllers that are typically placed outside the core, such as network controllers, cache memory and the system's main memory.
Intel, for instance, uses a front side bus to pump this information around. But as the company increases the core count on its processors, it also has to speed up the front side bus, which increases overall power consumption.
Tilera has moved all the controllers from the chipset to the processor, lining them up around the processor cores. Each processor core has a switch that routes the information between cores and the controllers.
One processing core and controller form one tile, which has five connections to neighbouring tiles, thereby forming a mesh network.
Each of the meshes is dedicated to one task, such as the input and output for the system's main memory or communications between each core's cache memory.
Sharing cache memory between the cores also prevents the need for large L3 caches, which tend to consume more power and can create traffic jams when accessed by multiple cores.
The mesh infrastructure allows Tilera to effortlessly increase and decrease the number of cores, creating faster and slower versions of the chip.
As the chip developer increases the number of cores, it also creates additional space for controllers around the cores.
This allows it to add memory controllers or PCI-express controllers and increase capacities depending on the chip's intended applications.
A chip relying on a front side bus, however, would not be able to use that component in lower or higher performance models. It would either be underpowered for a chip with additional cores, or a power hog for a smaller model.
The TILE64 processor introduces a new chip architecture, making it incompatible with Intel's and AMD's x86 processors. As a result, developers will have to recompile their applications.
The chip already supports SMP Linux, a Linux version specialised for parallel processing.
The company has also created developer tools that will recompile any application written in C for the new platform, although developers can expect additional performance gains if they further tweak their code.
Brookwood does not expect the new architecture to become an obstacle for the chip's adoption.
"In the days of Linux and everybody programming in C and C++ and Java, I do not think it is as big a obstacle as it would have been 10 years ago," he said.
Elements of the TILE64 processor are similar to other processors. Intel, for instance, has integrated a networking feature with each processor core for its Terascale processor, a research project that aims to build a functional 80-core chip.
The chip is merely a research project, however, and focuses on floating point operations that are common in scientific-style applications rather than the high throughput-style applications that Tilera is going after.
The processor might meet more competition from Sun Microsystems' T2 chip, which was unveiled earlier this month.
Better known by its Niagara 2 codename, the T2 features eight cores, each of which is capable of executing eight threads, making for a total of 64 simultaneous executions.
It too features some integrated controllers. Niagara 2 primarily targets applications such as web servers, but Sun is also looking to expand into the embedded space.
Although Tilera has a proven product and the reputation of an established system vendor, the firm expects to undercut the Niagara 2 price by roughly 50 per cent.
Sun has yet to reveal pricing information for its chip, but it is expected to sell at roughly the same price as its T1.