Researchers at Intel have crafted an early model of an 80-core processor, as part of the chipmaker's tera-scale computing project to build a super-fast parallel processor.
The test chip measures 275 square millimetres, making it about the same size as a current generation Xeon server processor.
It features roughly 100 million transistors, and is able to process 1.8 trillion instructions per second (commonly described as 1.8 teraflops) at top speed.
Intel stressed that the final product could be different from the test chip and could have more or fewer processing cores.
"We expect some of these technologies to become part of our product roadmap, but we do not see it going into all our products," said Gerry Bautista, director of tera-scale research at Intel.
The terra-scale project was unveiled at the Intel Developer Forum last September, and Intel plans to discuss details of its first working model at the Integrated Solid State Circuits Conference this week in San Francisco.
Each core is designed as a separate tile that combines a processing core with a networking router which connects the core to the four adjacent tiles.
This 'componentised' structure makes it easier to replace technologies on the chip in the future.
Intel's designers also removed the cache memory from the chip, intending to place memory directly under each core in a future design and connect it through the on-chip router.
The new memory placement allows for faster data transfer between the processing cores and memory.
It is also less expensive to manufacture because it allows Intel to produce the memory modules using a production process that is different from the processing cores.
To control the chip's power consumption, Intel divided each tile into 21 separate regions, each of which can be powered down independently.
The router component can go into a 'sleep mode' that cuts power consumption by 10 per cent, while still passing on data from other cores.
Memory modules can operate in a standby mode in which they retain their data while cutting power by 50 per cent, or be shut off entirely to cut consumption by 80 per cent.
The first teraflop chips are expected to reach manufacturing stage by 2010 to 2015. Although the current chip is able to perform basic operations, Intel and its partners have yet to complete multiple research projects.
The company plans to develop special cores for dedicated tasks such as cryptography, for instance, or to enhance virtualisation technologies in operating systems.
Software developers also need to update their programming techniques for software to function optimally on multi-core chips.
This is because two software components simultaneously claiming the same computing core could lead to a system crash.
Such incidents have led to power outages and other disruptions of critical utilities and services.
Intel chief executive Paul Otellini advertised the new chip in September as a solution for companies running very large data centres such as Google.
But Bautista claimed that a multi-core chip on this scale offers benefits to the average consumer as well. The chip could provide a powerful photo search application that allows users to look for images of people smiling, for instance.
It could also find applications in health monitoring systems to ensure that chronically ill or Alzheimer patients eat regular meals.
"This requires a level of artificial intelligence in the analysis that is well beyond simple image recognition today," said Bautista.
The new Intel chip specialises in so-called parallel processing, while current generation Pentium chips excel in sequential tasks.
The former is essentially the equivalent to building an 80-lane motorway, whereas the latter would be like constructing a single high speed road.
The challenge, however, is that a single complicated calculation will not benefit from a multi-core processor, in the same way that a lorry would not benefit from a multi-lane highway.