Expreview has the pretty pictures here, and the big news is a platform called Sabine in 2011.
Sabine is based on the Llano CPU, now called an APU, which the firm first mentioned last November.
Nothing seem to have changed on that front, but several things have been fleshed out. The first one is that it takes DDR3-1600, not exactly a stretch for two years out, but we will take it. The 32nm process is also a given, but one has to wonder if you will see something on that process from GlobalGoundries sometime in the preceding year. It should be ready long before Llano, and they don't have to wait for the CPU any more.
More interesting is the new socket, called FS1, and a BGA version for thin and light laptops. AMD is catching up to Intel here and that is a good thing. Socket height has always been a problem for AMD laptops. The slides also list 128-bit FP, but more on that in a bit.
Sabine uses the SB9xxM chipset, but who really cares? We say this because the GPU is in the CPU, so the 'chipset' is now really just a southbridge. For all of the people out there who think Nvidia has a future in the chipset business, look long and hard at this slide. Is a DAC, USB3, SATA, RAID, IR and clock generator chip a business that you would describe as IP leveraging or commodity? Chipsets are dead, between Sabine and Intel's MCMs, they are gone. The end.
Comparing the older stuff to what was presented in November, there are some detail changes. Danube, the 2010 notebook platform goes from S1g3 (Socket 1 gen 3) to S1g4, and supports only DDR3-1066. Is it a four-core part that pairs with the mobile version of the 8xx chipset. In this case, it is the RS880M north bridge and an unspecified SB8xxM south bridge. The integrated GPU will only be DX10.1, but the integrated paired part will almost assuredly be DX11.
That brings us to the odd bit, 128-bit FP. It is listed under all three cores, Caspian (2009), Danube (2010), and Llano (2011). My first thought was that it is 'SSE5' SIMD, and there are a lot of references to that in AMD CPUs, but this looks to be different. Is it IEEE 754R QP FP, or something SIMD oriented?
One theory is that Llano is one of the first Bulldozer cores, and they use what is called a cluster architecture. Since it has two Int units for each core and one shared FP, if the FP is double width, could there be some kind of SIMD functions for 'legacy' FP where it simulates 2 FP units? We will see, but the existence of it in current K10h cores make that a long shot.
In the end, we have a bit more info, and a big new puzzle. How long has the 128-bit FP been around for? Is it just not turned on yet because of standards wrangling, or is it more mysterious? And what does this have to do with the NSA and spy satellites?1 I for one can't wait for the new cores, they are long overdue.
1 Nothing, I just made that part up. If you ask AMD, they will most likely deny it anyway though.