Specialised hardware will also emerge in the form of co-processors. AMD’s Torrenza initiative will open up the HyperTransport bus to allow first or
third party co-processors to access the same transport ring as the CPU and memory. While this is initially envisioned as a technology for the workstation and server market, there’s no reason why we couldn’t see physics or 3D rendering co-processors working hand-in-hand with a next-generation Athlon. And if this sort of functionality proves its worth, it could easily make the transition onto the CPU.
‘The cases where we’ll see that, of course, will be the ones where there’s real demonstrable value,’ says Moore, ‘particularly something that would help the power efficiency of the chip itself. If, rather than running tons of code to accomplish some function, we can put a special piece of hardware on board to do it much more efficiently, that helps the whole power efficiency.’
Intel is thinking along similar lines and plans to incorporate dedicated hardware for a variety of tasks, including 3D graphics rendering, digital signal processing and natural language processing.
Of course, a multicore architecture provides other options. Phil Emma believes that, because people expect processors to do diverse things, it might make sense to design some cores for specific applications. ‘In addition to multicore, those things you call cores might be different sorts of things.’ In short, cores don’t have to be general purpose. Intel will design processors that allow dynamic reconfiguration of the cores, interconnects and caches to meet diverse and changing requirements. Such changes could be made at the fab or by an OEM, but most excitingly Intel talks of reconfiguration at runtime, the CPU adapting to support applications on-the-fly.
This sort of flexibility is a hallmark of next-generation CPUs. Both Chuck Moore and Phil Emma talk of virtualisation as a key technology, enabling one physical machine to appear in various configurations – as multiple discrete systems or as a single out-of-order powerhouse machine – to match the needs of the app in hand. AMD has already experimented with technologies that make multiple cores appear as a super-powered single core at OS level.
New pressures
The magic combination of multicore, specialised hardware and virtualisation will also bring new challenges. Phil Emma says, ‘We’re going to have much more pressure put on the on-chip storage and the off-chip bandwidth, which is required to bring the content into that storage.’ Future high-capacity caches might initially use 1T of DRAM, a high-speed memory technology, then evolve towards 3D memory structures with multiple planes of circuitry. Alternatively, AMD has licensed Z-RAM: a form of embedded memory that can achieve five times the memory density of the embedded SRAM used in today’s on-chip caches.
Also, the transport links will have to get faster. Technologies like AMD’s HyperTransport 3 will help, boosting FSB bandwidth from 2.8 to 5.2 GigaTransfers per second, but the real future is probably optical, using light rather than electrons to transfer data across the system bus (see boxout, overleaf).
Of course, the central issues governing CPUs in the future will be the same as now: heat and power. As processors scale down in size from 65nm to 45nm to 32nm, the power density goes up to levels where it might adversely affect performance. And while a die-shrink means an identical processor will consume less power and produce less heat, clock it up and you eventually reach a point where it becomes uneconomical to power and cool it. As a result, CPUs will have to get even smarter about their power management. Both Core 2 Duo and K8L show a partitioned view of power management, where parts of the chip can be shut off when not in use.
There’s no doubt that heat and power will eventually stretch silicon beyond its limits, and not every part of the processor can get smaller. As Ghavam Shahidi, director of Silicon Technology at IBM’s Thomas J Watson Research Center, notes, ‘As processes change from 90nm to 65nm to 45nm and beyond, everything shrinks, but some things can’t shrink any more. One of these is the gate oxide [the insulating material used to form a transistor gate], which at just 11 angstroms can’t be made any smaller than it is right now. Moving from 90nm to 65nm to 45nm, for the first time we’re not making these gate oxides smaller. And as they move forward, we may not be able to make some of the other material thicknesses as small as we’d like to.’