It’s not just PC Authority that’s celebrating 10 years – last year also marked the tenth year of Intel’s Developer Forum (IDF). At that first IDF, the cutting-edge was the Pentium 2 with 350nm architecture. Of course, back then everyone was talking in micrometres rather than nanometres, so they called it 0.35 microns, which sounds smaller. At that first IDF, Intel also announced that planning that was well under way to bring 0.25 micron architecture to market within 18 months.
But even in 1997 Gordon Moore could see limits to the existing silicon technology. He predicted that we were likely to hit the limits of the manufacturing industry’s ability to shrink transistors: “Some time in the next several years we get to some finite limits, but not before we get through five generations,”
Five generations of processors later – 250nm, 180nm, 130nm, 90nm and 65nm – and Intel has reached some of the limits of silicon wafers. Thanks to visionaries like Gordon Moore, though, Intel also worked on solving the problems: in the next few weeks, we’ll see systems based on processors designed around the 45nm “Penryn” process (that’s 0.045 microns in 1997-speak). This shift has only been made possible thanks to a move away from silicon, via what Intel calls “High-K” gate dielectric technology.Breaking the size barrier
Microprocessors are made of hundreds of thousands of transistors connected together by metal wire to form an integrated circuit. Silicon dioxide is “grown” on top of a silicon wafer to act as a gate that prevents or enables electrical current to pass from the wafer through to the metal wires. Once that layer is grown, the silicon wafer – through a lengthy process involving over 300 steps – is essentially stamped with circuit patterns.
As processors get smaller, the layer between the silicon wafer and the metal gate of a transistor – called the gate dielectric – gets thinner and leaks more energy from the transistor. Increased leakage also means more heat is dissipated, so you get inefficient and hotter processors as you reduce the size of transistors.
In the 65nm Core Duo processors, the silicon dioxide-based gate dielectric is a mere five atoms wide. Intel shrink the transistor about 30% in all dimensions from one generation of processors to the next – every two years – and Intel’s research showed that making the gate dielectric any thinner than five atoms would increase energy leakage without improving performance.
That meant getting rid of silicon dioxide and finding a replacement material for the gate dielectric in the new 45nm technology.
Intel’s Kahizad Mistry describes what a massive undertaking that was: “What’s unique and significant about Intel’s 45nm technology is that for the first time in 40 years we’ve changed some of the basic materials that are used to fabricate the transistor.”
The roadmap for creating a new process technology isn’t a fast one, even without changes to the basic transistor materials. Electrical engineers meet to determine the design, performance and power goals for the processor and transistor, as well as the process and environmental goals for manufacturing up to ten years in advance. For 45nm, the materials group experimented with several compounds to find one that had the right chemical, electrical and physical properties.
The initial research into High-K metal gates started in the late 90s, and in 2003 Intel selected Hafnium Dioxide as the compound of choice for their 45nm processors and the generation beyond. Hafnium Dioxide wasn’t the only compound being tested, and we may see further compounds being used in future. But for 2007, 2008 and 2009, Hafnium – and High-K – is where it’s at. “It helps to extend Moores law into 45nm and beyond,” said Mistry. In addition to changing the gate dielectric, Intel have changed the polysilicon gate to a new metal gate.From research to reality
The research and development teams for 45nm worked together with the compounds the materials group had selected for about a year and a half, doing what’s called ‘path-finding’ – testing how to bring the materials into the process of wafer construction and chip architecture. Intel’s teams design for manufacturability by creating the test chip and tens of thousands of structures that help evaluate design robustness, circuit blocks that we characterize during development. Both process and design are worked upon simultaneously. Once the design rules and transistor performance are defined, the team at Intel creates a couple of working chip designs.
The next step was to create a test chip. This test chip includes structures that help determine the success of the manufacturing process: a lot of special digital and analogue circuits, and also a dense static ram (SRAM) array. The SRAM array is a starting point because it uses fewer steps in production than microprocessors. This lets the engineers check that technology is ready, that the yields are good and that the entire manufacturing process is workable on a large scale.
“It wasn’t until early 2006 that we had one or two working chips and converted one or two billion transistors with 45nm. The SRAM test chip was produced late 2005 with these new materials integrated. That chip was what we used to check that the tech was ready, that the process yields well,“ said Mistry.
The biggest advantage of moving from 65nm to 45 nm, apart from the cost improvement (you can fit twice as many transistors onto a die or make the chip size smaller for the same number of transistors), is power efficiency. Intel estimates that a given computer function will use 30% less power with a Penryn-based chip. That power efficiency means that we’ll see Penryn in everything from ultramobile laptops through to high performance servers.